Processor-Driven Verification IP for SoC Verification
Kozio has taken a decade of verification experience at the board level and is applying it to verification at the chip level. When you are ready to verify the interaction of one or more processor cores with other on-chip IP blocks, Kozio’s solution is ready and allows you to start using processor-driven verification without having to write test code. The beauty of the Kozio solution is that it provides a continuity of verification from simulation to final silicon, including a solution usable for production testing of new products using your chip design.
At the core of the Kozio solution is a third-generation Verification and Test OS (VTOS™). This is a bare-metal OS that includes an interpreter, remote access, functional tests, low-level control, execution tracing, and other features designed from the start to automate verification and simplify troubleshooting while greatly reducing the hours spent under simulation or emulation.
VTOS provides the capability to quickly generate stimulus from a processor core through on-chip IP blocks as well as monitoring IP Blocks when stimulus is generated from outside the chip under test. VTOS is embedded software that is easy to configure for your chip design. VTOS’ offloading and minimal footprint provide the optimal processor-driven verification under simulation or emulation.
Use your current simulation environment and our SystemVerilog to DPI wrapper to make VTOS command calls from your testbench. Kozio’s solution has been configured and tested using the leading simulators from Cadence, Mentor Graphics, and Synopsys.
Configure VTOS for simulation using VTOS Builder – existing configuration data can be reused with minimal porting effort.
Kozio integrates VTOS under simulation, working side-by-side with your engineers.
Kozio provides a SystemVerilog wrapper for easy testbench integration with embedded verification software.
Running VTOS under simulation will provide a quicker verification of the next chip with reduced test bench effort and no delays.
If you include FPGA emulation as one of your verification steps, VTOS project information and test scenarios are all shareable from simulation to emulation with minimal changes. The flexibility and run-time extensibility of VTOS provide an excellent platform for verifying on-chip IP blocks and can be quickly tuned to meet your emulation platform requirements.
Configure VTOS DUT for FPGA Emulation using VTOS Builder – emulation setup totally prepares the environment for chip bring-up.
Use VTOS to verify the development board and software test environment prior to chip bring-up.
Automate regression testing for all emulation platforms, the same test scenarios can be run against all platforms providing a quick regression test.
SoC Bring-up and Debug
Tapeout is complete and the wait begins. Successful teams create a validation board that they use for chip bring-up. Those teams validate the board design, and all off-chip peripherals, using an older processor or FPGA emulation board with an interposer. Verifying that the validation board design is without issues helps reduce the time and risk of chip wake-up. It is also common for teams to create reference board designs that they will share with customers, allowing the potential customers to evaluate the new chip as soon as possible after bring-up.
Validating these additional board designs adds development time and effort into the schedule. Kozio's VTOS provides a common solution for verifying these new board designs, reusing any scripts, drivers and tests created during simulation or emulation. In fact, the VTOS project and configuration data can also be shared from earlier verification steps reducing the preparation time to a couple hours. Using VTOS allows you to reuse the same solution across verification stages, providing flexibility and great coverage that will reduce the time and risk of chip bring-up and validating new design boards.