Production Test

Declining Fault Coverage

Structural test coverage is declining due to advanced packaging and PCB technologies like High Density Interconnect (HDI) which are limiting test access points. The lack of test point access is directly affecting fault coverage. Fault coverage has fallen to below 50% for many high density products. Not very long ago typical fault coverage was in the 85-95% range.

The Software Boot Problem

A symptom of the falling test coverage is the software boot problem. ICT and Boundary Scan tests may PASS but the Bootloader or OS will not boot without any indication why. Software boot requires much of the board to be operational – particularly RAM. The lack of test coverage creates a test vulnerability that can be costly and time consuming. Not only does the board not boot, the reason for the boot failure is unknown.

DDR memory does not have Boundary Scan support and is very sensitive to timing margins. DDR memory can be a common cause of boot failures and undetectable given current methods.

Embedded Test Solution

Embedded Test is complementary to ICT and Boundary Scan. The Embedded Test phase resides between the structural test phase the software boot phase providing a low level subsystem test pass. The embedded test program actually executes on the Unit Under Test (UUT) but has a very limited dependency on the board being fully operational. Today the Embedded Test executes out of on-chip memory, eliminating all DDR dependencies.

Board Scan

A Board Scan is an Embedded Test that verifies the basic operations of all boot devices and hardware interfaces. The Board Scan software is a small and lightweight configurable test program. Board Scan is configured for your particular board by adding devices to each of the available busses. For instance, a user would add a device to the SPI, I2C, PCI, and other busses with configuration information. Here is an example:

  1. I2C Device
    • Device Name
    • Reference Designator
    • Device Address
    • Device Size
    • Speed
  2. PCI Device
    • Device Name
    • Reference Designator
    • Device Address
    • Vendor Id

After configuration is complete, Board Scan is loaded on the UUT and begins execution. In a matter of seconds, Board Scan will verify the basic operation of all the busses and the devices on those busses. Any components that fail to communicate with Board Scan are identified as a defective and Board Scan will report the Reference Designator.

Improve OS Boot Predictability

Because the Embedded Test is actually executing on the processor with minimal dependencies, the test are running at full processor speed and can selectively test different components on the board as defined during configuration. This test strategy verifies the board is fundamentally operational with a high probability of booting the Bootloader and then the Application OS.

The Board Scan will improve OS boot predictability and quickly identify faults that would prevent an OS boot. ICT and Boundary Scan alone will not be able to detect component failures that might prevent an OS boot.

Final Assembly Testing

Embedded Test can provide a test option for products that are fully assembled. The assembly process may have been partially completed (loose connector) or damaged the PCB. Embedded Test can be extended to include more subsystem test at a higher level to verify USB, display or audio codec operation. The user can decide the depth and breadth of desired coverage.

Related Kozio Products

  • VTOS DDR™ provides an Embedded Test solution for DDR SDRAM
  • VTOS Program™ provides an Embedded Test solution for programming any programmable device
  • VTOS Scan™ provides an Board Scan solution for all boot devices and all hardware interfaces



  • Cut production boot and test time to less than 10 seconds
  • Covers the gaps left by ICT and Boundary Scan
  • Easy integration with your current test system using vAccess™
  • Save time and expense by leveraging the test platform used by design engineering
  • Use on-board processor to program Flash or FPGA, saving minutes
  • Optimize test time and programming time using task-focused user interfaces
  • Fast fault isolation and debugging of bad boards